Electronic matrix arrays find considerable application in systems such as, for example, liquid crystal displays and high density memories. Such systems generally include X and Y address lines which are vertically spaced apart and cross at an angle to form a plurality of crossover points. Associated with each crossover point is an element to be selectively addressed. The elements can be, for example, the liquid crystal display pixels of a liquid crystal display or the memory cells of an electronically addressable memory array.
Some form of isolation device is generally associated with each array element. The isolation elements permit the individual elements to be selectively addressed by the application of suitable read potentials between respective pairs of the X and Y address lines.
Amorphous semiconductor thin film field effect transistors have found wide usage for the isolation devices in such arrays. Thin film field effect transistors formed from deposited semiconductors, such as amorphous silicon alloys are ideally suited for such applications because they exhibit a very high dark resistivity and therefore have very low reverse leakage currents. The reverse leakage currents are so low that very high on to off current ratios are made possible for effectively isolating the non-addressed array elements from the array elements being addressed.
While thin film field effect transistors formed from amorphous semiconductor alloys are ideally suited as isolation devices in addressable arrays, they are not so ideally suited for use in forming the addressing circuitry required for the selective addressing of the array elements. One reason for this is that these devices have not exhibited the switching speeds required for these applications.
For many applications, the components forming the addressing circuitry of electronically addressable arrays are required to switch at video rates, on the order of 50 megahertz, for example. Such is the case particularly in liquid crystal displays or fast read-out memories. Structurally, thin film field effect transistors generally include source and drain electrodes, a semiconductor material between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. Current flow through the transistor between the source and drain is controlled by the application of a voltage to the gate electrode. The voltage on the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which the device current is conducted.
In thin film field effect transistors, both output current and operating speed are directly related to the structural configurations of the devices and to the field effect mobility of the semiconductor material. The output current is directly proportional to the field effect mobility and is almost always inversely proportional to the current conduction channel length. The maximum operating frequency of such a device is related to the channel length which is fixed by the spacing between the source and drain electrodes in a more complicated manner. The reason for this is that the operating frequency is not only related to the channel length, but is also dependent upon the total capacitance of the device. The total capacitance has basically two components, a fixed capacitance due to electrode overlap, and a dynamic capacitance that results when the current conduction channel is formed. The fixed capacitance is a direct function of the electrode overlap. The dynamic capacitance however is inversely proportional to the channel length. Since both the output current and the dynamic capacitance are both inversely proportional to the channel length, the maximum operating frequency should be inversely proportional to the square of the channel length if the fixed capacitance is disregarded. Unfortunately, the fixed capacitance cannot be disregarded. As a result, as long as there remains some fixed capacitance, the total expected improvement in device speed with reduced channel length cannot be realized. For this reason, even though a thin film field effect transistor may have a narrow channel, the frequency response of the device can still be limited by the fixed capacitance and the field effect mobility. The fixed capacitance can be the result of device design or process constraints imposed by limited photolithographic resolution. The field effect mobility is generally fixed by the type of semiconductor used to form the device and is generally low for amorphous semiconductor alloy devices.
Thin film field effect transistors have been made by processes including conventional 10 micron photolithography. Such conventional processes have resulted in minimum channel lengths on the order of the conventional feature size of 10 microns. Such channel lengths with the field effect mobilities of amorphous semiconductor alloys have resulted in relatively slow speed devices. One way to overcome the limitations inherent in conventional photolithographic resolution is to utilize a vertical structure where the current conduction channel length is determined by the vertical separation of the source and drain electrodes, as described and claimed in commonly assigned copending U.S. patent application Ser. No. 529,299 for Thin Film Transistor, filed in the names of Richard A. Flasck, et al. The transistor therein disclosed includes source and drain regions vertically displaced with respect to each other relative to a substrate and having a deposited semiconductor therebetween. The length of the current conduction channel is a function of the vertical displacement distance between the source and drain electrodes and is substantially independent of the constraints otherwise imposed by standard 10 micron photolithography.
The aforementioned U.S. patent application Ser. No. 529,299 of Richard A. Flasck, et al., for Thin Film Transistor is a continuation of U.S. patent application Ser. No. 280,378, filed Nov. 19, 1980, for Thin Film Transistor, which in turn was a continuation of application Ser. No. 103,011, filed Dec. 13, 1979, for Deposited Film Memory Systems.
Further improvements in vertically arrayed thin film field effect transistor structures are described in the commonly assigned copending U.S. patent application Ser. No. 549,996 of Hellmut Fritsche, et al., filed Nov. 8, 1983 for High Performance, High Voltage, Small Area Thin Film Transistor and Method of Making Same. The vertical thin film field effect transistor therein disclosed includes source and drain electrodes vertically displaced with respect to each other and relative to a substrate, with an insulating layer therebetween. A semiconductor extends along the non-coplanar or diagonal edges of the source and drain electrodes and the insulating layer.
Further, improvements in vertically arrayed thin film field effect transistor structures are described in the commonly assigned copending U.S. patent application Ser. No. 550,234 of Zvi Yaniv, et al., filed on Nov. 8, 1983, for High Performance Thin Film Transistor Having Improved Carrier Injection. The transistor therein disclosed includes source and drain electrodes vertically displaced with respect to each other relative to a substrate, with a deposited semiconductor extending along the non-coplanar or diagonal edges of the source and drain electrodes, wherein the contacts between the semiconductor and the source and drain electrodes include an ohmic contact enhancement means incorporated therein. Further improvements in vertical thin film field effect transistor structures are described in the commonly assigned copending U.S. patent application Ser. No. 549,979 of Gregory Hansell, et al., filed on Nov. 8, 1983 for Thin Film Transistor Having Annealed Gate Oxide and Method of Making Same. The transistors therein disclosed have an annealed insulator layer between the gate electrode and the semiconductor.
Common to all of the above described field effect transistors is a vertical structure, that is, a structure where the drain is vertically displaced from the source. All of these transistor structures provide a current conduction channel length of one micron or less while still allowing the use of conventional photolithography during the fabrication of the devices.
A horizontal thin film field effect transistor having a short current conduction channel in a deposited semiconductor between closely spaced source and drain electrodes is fully described in copending and commonly assigned U.S. patent application Ser. No. 557,773, filed on Dec. 5, 1983 in the names of Mohshi Yang and David Vesey, for Short Channel Thin Film Field Effect Transistor. This transistor has a generally horizontal structure. The source and drain electrodes are in contact with a semiconductor, and separated from each other by a dimension less than the feature size of conventional photolithographic processes.
As described therein, the source and drain electrodes are formed by forming a thick film of photoresist over a first electrode material, exposing the photoresist through a photomask, developing the photoresist, etching the underlying electrode material to undercut the photoresist to form one electrode, and thereafter, without removal of the remaining photoresist, shadow depositing the other electrode. The shadow deposition is carried out from a unidirectional or collimated source. As a result, deposition is avoided within the shadow of the photoresist which can be on the order of one micron or less in dimension to form the closely spaced source and drain electrodes.
While the transistor and process described immediately above provide significant improvements to planar or generally horizontal thin film field effect transistors, there remains some overlap of the drain and source electrodes with the gate electrode. It has been determined that even though these devices are capable of operating at speeds not heretofore possible for planar thin film field effect transistors, the fixed capacitance of the devices limits the operating speeds thereof to a point where all of the advantages of the short current conduction channel lengths cannot be fully obtained.
A further improvement in thin film field effect structures is disclosed in commonly assigned copending U.S. patent application Ser. No. 590,836, of Zvi Yaniv et al., filed Mar. 19, 1984, for Improved Reduced Capacitance Narrow Channel Thin Film Transistor And Method Of Making Same. The transistor structure there disclosed provides a thin film field effect transistor having substantially reduced capacitance as a result of having virtually no drain and source electrode overlap with the gate electrode while having a narrow current conduction channel. The transistor includes an insulative substrate, a gate electrode formed on the substrate, wherein the gate electrode has a minor dimension of about one micron or less. The transistor further includes a gate insulator overlying the gate electrode, and source and drain electrodes disposed over the gate insulator in non-overlapping relation to the gate and being spaced apart by a distance substantially equal to the gate minor dimension. A layer of semiconductor material is disposed between the source and drain electrodes in electrical connection therewith.
Each of the foregoing transistor structures disclosed in the above-referenced applications, which are assigned to the assignee of the present invention, represents a significant improvement in the amorphous semiconductor alloy thin film field effect transistor art. However, as previously mentioned, the switching speeds of these devices are not only dependent upon device configuration, but also are directly dependent upon the field effect mobility of the semiconductor through which the device current must pass. Unfortunately, amorphous semiconductor alloys exhibit relatively low field effect mobilities on the order of 0.1 to 1. Hence, even though improved device configurations have been made possible as described above, the field effect mobilities of these devices essentially preclude their use in applications such as in addressing circuitry, where video rate switching is often required.
In summary, while amorphous semiconductor alloy thin film field effect transistors are ideally suited for many applications, such as for isolating matrix array elements to be selectively addressed, they are not suited for use in applications where video rate switching is required in association with other components which would be adversely affected by the processing of the devices. For this particular and important application, a new and improved thin film field effect transistor is required. The improved transistor must include a semiconductor material having high field effect mobility. It preferably should be adapted to be fabricated using commercially acceptable processes and conventional 10 micron photolithography permitting large area application while still exhibiting fast switching rates at, for example, video rates of about 50 Mhz.
Thin film transistors have been made with polycrystalline silicon and reported in the literature. See for example, "Thin-film transistors on molecular-beam-deposited polycrystalline silicon", Matsui et. al., 55 J. Applied Physics 1590, Mar. 15, 1984. Matsui disclosed a thin film transistor with source and drain regions formed in polycrystalline silicon by ion implantation which is generally not a commercially acceptable process.